| 01 |
U1 |
Von Newman model |
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| 02 |
U1 |
Various subsystems, CPU |
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| 03 |
U1 |
I/O, System Bus |
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| 04 |
U1 |
CPU and Memory registers Program Counter, Accumulator, Instruction register |
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| 05 |
U1 |
Micro-operations, Register Transfer Language, |
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| 06 |
U1 |
Instruction Fetch, decode and execution |
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| 07 |
U1 |
Data movement, Manipulation, Instruction formats |
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| 08 |
U1 |
Addressing modes of basic computer |
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| 09 |
U1 |
8085 microprocessor organization |
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| 10 |
U1 |
Revision |
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| 11 |
U2 |
Control Unit Organization: Hardwired control unit |
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| 12 |
U2 |
Micro and nano programmed control unit, |
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| 13 |
U2 |
Control Memory, Address Sequencing |
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| 14 |
U2 |
Micro Instruction formats |
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| 15 |
U2 |
Micro program sequencer, Microprogramming, |
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| 16 |
U2 |
Arithmetic and Logic Unit: Arithmetic Processor, Addition, subtraction, |
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| 17 |
U2 |
Multiplication and division |
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| 18 |
U2 |
Floating point and decimal arithmetic |
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| 19 |
U2 |
Arithmetic units |
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| 20 |
U2 |
Design of arithmetic unit. |
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| 21 |
U2 |
Numerical |
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| 22 |
U2 |
Revision |
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| 23 |
U3 |
Modes of data transfer – program controlled Interrupt driven direct memory access, |
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| 24 |
U3 |
Direct memory access, |
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| 25 |
U3 |
Interrupt structures, I/O Interface |
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| 26 |
U3 |
Asynchronous data transfer |
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| 27 |
U3 |
I/O processor,8085 I/O structure, |
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| 28 |
U3 |
8085 instruction set and basic programming. |
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| 29 |
U3 |
Data transfer – Serial / parallel, synchronous/asynchronous, Simplex/half duplex and full duplex. |
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| 30 |
U3 |
Revision |
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| 31 |
U4 |
Memory organization: Memory Maps, Memory Hierarchy |
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| 32 |
U4 |
Cache Memory – Organization and mappings. |
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| 33 |
U4 |
Cache Memory – Organization and mappings. |
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| 34 |
U4 |
Associative memory |
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| 35 |
U4 |
Virtual memory |
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| 36 |
U4 |
Page Fault, Demand Paging, Swapping |
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| 37 |
U4 |
Memory Management Hardware. |
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| 38 |
U4 |
Memory Management Hardware. |
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| 39 |
U5 |
Multiprocessors: Pipeline and Vector processing, |
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| 40 |
U5 |
Instruction and arithmetic pipelines, |
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| 41 |
U5 |
Vector and array processors, Interconnection structure, Interprocess Communication |
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